Embodiments of the inventive subject matter generally relate to the field of computers, and, more particularly, to utilizing a load stall interrupt in a computer to indicate a long lasting memory operation.
As processing cores or threads (CPUs) have become both faster and plentiful, they have proven to overwhelm the memory subsystems that currently exist. These subsystems use various technologies in order to minimize the average and aggregate cost of accessing memory, the most popular of these is the “memory cache”. Caches are faster, and “closer” memory that is limited in size but is normally inclusive of the larger store. Caches can be arranged at several “levels”, each getting smaller and faster as they cache the level below. It is common practice for hardware to “switch” to another compute resource (integer, SIMD unit, etc.) in order to minimize the amortized impact of memory latency.
Some memory/storage subsystems can be so large and/or complex, that the latency to access the data may be unbounded, or beyond the reasonable expectations of the CPU. The failure to meet these expectations may be confused as an error or could result in large periods of power or computational inefficiency.